Boundary Scan Architecture for a Double Precision Floating Point Subtractor


Anirudh Kashyap
Student, R.V. College of Engineering, Bengaluru.

Kusuma Keerthi
Head of Skill Development, Silival Pvt. Ltd., Bengaluru.

Dr. Shilpa D.R.
Associate Professor, R.V. College of Engineering, Bengaluru.


The boundary scan logic for testing was developed in order to make the process of testing easier for System-on-Chip (SoC) [1] architectures. The proposed work focuses on designing a boundary scan logic for a 64-bit floating-point subtractor unit. The TAP controller designed is capable of executing the three mandatory Joint Test Action Group (JTAG) instructions of the IEEE 1149 standard. The testing architecture has the potential to not only test the functionality of the core logic but also to test single stuck-at faults for all the inputs and outputs of the core logic. A provision for bypassing the core logic was made in order to skip the IC while testing numerous ICs together. A simulation was also performed to demonstrate the above procedures. The designed module can further be used in a larger circuit with other ICs [2]containing a similar boundary scan structure with individual TAP controllers.