VLSI Architecture Design and Implementation of CANNY Edge Detection


Vana Sundari M, Student, M.E, Rammohan T, Professor
Applied Electronics.
Santhosh B K , Rajamoorthy P , Jayaprakash V, Assistant Professor
Department of Electronics and Communication Engineering, Jaya Engineering College, Chennai.


In One of the most essential methods in digital image processing is edge detection. Because of its capacity to detect edges even in images heavily contaminated by noise, the Canny edge detector is the most widely used edge detection algorithm. A modified canny edge detector is created in MATLAB and implemented in FPGA in this project. The mask is used for gradient calculation, and bilinear interpolation of four pixels is used in non-maximal suppression. In the iris detection subsystem, this edge detector is used as a pre-processing stage. The goal of creating the hardware modules for the canny edge detector was to minimise its complexity, improve its performance, and make it appropriate for VLSI implementation on a reconfigurable FPGA-based platform.