A Reconfigurable Variable Resolution Digital Architecture for Diverse Analog to Digital Converters

The bottlenecking role of Analog to Digital Converters (ADCs), while using it in variety of applications, is well known to the designer since past. This stimulates to have a universal ADC architecture which can satisfy needs of diversified applications. The work presented in this paper is based on this thought and successfully demonstrates, ‘Xilinx Spartan 3E’ FPGA based, hardware realization of a Reconfigurable Digital Section Architecture that can be configured for Multiple iterative type of Analog to Digital Converters (ADCs). This single reconfigurable architecture has provided compatibility to interface with analog sections of three different architectures i.e. Successive Approximation ADC or Single Stage Pipeline ADC with feedback or Dual Slope ADC and empowers variable resolution up to 8 bits. This facilitates flexibility in application specific selection of suitable ADC architecture and thus increases diverse application areas at the cost of design complexity. The architecture utilizes 2.5 % of total gate count and 27% input output blocks of FPGA while operating at 30 MHz clock frequency. The on-chip power consumption is 54.93 mW. The results show reduction in effective power utilization, pin count and clock skew without scarifying operating speed as compared to single time multiplexed Digital architecture for these ADCs, synthesized on the same FPGA.