Dr. Kendaganna Swamy S, Dr. Rajasree P M, Anand M Sharma, Jnanaprakash J Naik
Dept. of Electronics and Instrumentation, R V College of Engineering Bengaluru, India.
A Review Paper on Memory Fault Models and its Algorithms
Authors
Abstract
The significance of testing semiconductor
memories has surged in the industry due to the higher density of
modern memory chips. This paper investigates functional faults
prevalent in today’s memory technology: coupling faults,
address decoder faults, transition faults, stuck-at faults, and
neighbourhood pattern-sensitive faults. It delves into techniques
to identify these issues, focusing on zero-one, checkerboard, and
March pattern tests across chip, array, and board levels. The
study explores test algorithms, assessing fault coverage. Overall,
it offers insights into challenges posed by dense memory chips
and a comprehensive analysis of functional faults. Notably,
MARCH algorithms outperform others in fault coverage, power
efficiency, area optimization, and time complexity, suggesting
their preference for reliable high-performance memory devices
in the electronics industry.