Area Efficient Modified Array Multiplier


P Akshatha Shetty
Department of ECE R.V. College of Engineering Bengaluru ,India.
Dr. Kiran V, Professor
Department ECE R.V. College of Engineering Bengaluru, India.


Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.