Enhanced Floor plan Algorithm for Ultra Complex SoC’s

With the increase in the functionalities, complexity and instance count of the designs, floor planning has become a most critical task which needs lot of manual effort, time and machine usage. As the technology of shrinking, there are analog circuits which are dominating the chips; there are lot of floor plan rules which is mandatory and need to be done manually and it takes time, energy and manpower which is being costly. We are developing the algorithm of enhanced automatic floor plan by honoring all the floor plan rules and allowing the power and area optimizations.