Implementation of a Parallel Fault Simulation System using PODEM in a Hardware Accelerator using Python


Mahesh Bhat K, Namita Palecha, Assistant Professor
Department of Electronics and Communication Engineering, RV College of Engineering, Bangalore.


VLSI Testing is one of the essential domains in recent times. With the channel length of the transistor decreasing continually, the number of transistors in a chip increases, thus increasing the probability of defects or faults. Automatic Test Pattern Generator is one way to find such input test vectors to the circuit, which will help identify the faults if present. PODEM algorithm is one such algorithm used in this regard. This paper helps in reducing the runtime of this algorithm by the parallelism approach. Different stuck-at faults in the gate level circuit are simulated parallelly.