Palagiri Kartheek, PG Scholar
Department of ECE, VEMU Institute of Technology, P.Kothakota, Andhra Pradesh, India.
R.Rani, Assistant professor
Department of ECE, VEMU Institute of Technology, P.Kothakota, Andhra Pradesh, India
Implementation of Modified folded Cascode OTA in Different Biasings Voltages
Authors
Abstract
This paper presents an optimized methodology to modified folded Cascode operational trans conductance amplifier (OTA)
design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID
methodology in order to optimize MOS transistor sizing. This new family of OTA designs is suitable for biomedical and healthcare
circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the stateof-
the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch
biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltagecombiners
specifically targeting low voltage applications. The folded voltage-combiners biased OTA is able to operate correctly under a
voltage supply down to 0.7 V with proper DC biasing. The simulation is performed in HSPICE Synopsys Tool and compared with
existing designs.