Novel Approach to Measure Internal Power Domain PG Route Weakness

Grid weakness measurement is an extremely important process in the modern-day VLSI design flow. In designs that contain power gating switches, there are additional challenges. It is desirable to find the PG grid weakness of only the gated domain. The tools used in the industry typically measure the total voltage drops from the bump location to the transistor pin. This voltage drop is the summation of the voltage drops in the external domain, switch pin network, and internal domain. This paper explores the ways to measure the internal pin domain voltage exclusively. Ansys Totem tool is used for simulation. Finally, the simulation results are presented to propose the effectiveness and accuracy of the given solution.