Real Time Implementation of Video Compression Based on DWT


Dr. Pramod Kumar Naik
Shell India Pvt Ltd, Bangalore, Karnataka, India.
Vyasaraj T, Assistant Professor
Dept of ECE, BNMIT, Bengaluru, VTU, Belagavi Karnataka India.
Ramachandra Ballary
TCE department, BMS College of Engineering, Bengaluru, Karnataka India.


In this paper highly efficient 3D Discrete Wavelet Transform architecture is designed and implemented on seven series FPGA. The throughput is analyzed and its performance matrices are compared with different video file format. Today top of the line high-end image and video consume huge amount of memory. The designed architecture of DWT based video compression is again executed in parallel processing mode and its execution time is tabulated demonstrates reduced the processing or execution time. This paper demonstrates the superiority of the designed architecture both in normal mode of execution and parallel processing mode of execution .We know that higher the throughput of the video processing design results in Low power consumption. The Internal Architecture of the design is explained in brief and is synthesized in Xilinx Vivado 17.4 and implemented on Zed board. Based on the experimental results of the design being implemented on FPGA, demonstrates the memory saving capabilities and superiority of this architecture. The resultant architecture has drastically reduced latency and has enhanced the speed of operation.